Method for fabricating nonvolatile memory device

ABSTRACT

Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.

CROSS REFERENCE TO RELATED APPLICATION

This is a divisional application based on pending application Ser. No.12/894,615, filed Sep. 30, 2010, the entire contents of which is herebyincorporated by reference.

BACKGROUND

1. Field

The present disclosure herein relates to a nonvolatile memory device anda method for fabricating the same, and more particularly, to anonvolatile memory device having a three-dimensional structure and amethod for fabricating the same.

2. Description of the Related Art

The degree of integration of semiconductor devices needs to be increasedto meet consumer demands for excellent performance and low prices. Insemiconductor memory devices, since the degree of integration is animportant factor affecting the price of products, increasing the degreeof integration is of particular importance. In typical two dimensionalor planar semiconductor devices, since the degree of integration ismainly determined by the area occupied by a unit memory cell, the degreeof integration is greatly affected by the level of technologies offorming a micro pattern. Further, miniaturization of patterns requireshighly expensive equipment. The degree of integration of two-dimensionalsemiconductor memory devices is being steadily increased, but there arelimits.

Three-dimensional semiconductor memory devices includingthree-dimensionally arranged memory cells are being proposed. Processingtechnologies that can reduce the manufacturing cost per bit to less thanthat of the two-dimensional semiconductor memory device and achievereliable product characteristics are required for mass production ofthree-dimensional semiconductor memory devices.

SUMMARY

Embodiments are therefore directed to nonvolatile memory devices andmethods for fabricating such nonvolatile memory devices, whichsubstantially overcome one or more of the problems due to thelimitations and disadvantages of the related art.

It is therefore a feature of an embodiment to provide a non-volatilememory devices having a three-dimensional structure with improvedelectrical characteristics relative to the comparable conventional art.

It is therefore a separate feature of an embodiment to provide a methodfor fabricating a NAND-type nonvolatile memory device having athree-dimensional structure with improved electrical characteristicsrelative to the comparable conventional art.

It is therefore a separate feature of an embodiment to provide anonvolatile memory device and a method for fabricating such a memorydevice in which a channel connection region induced by a fixed chargelayer is provided to the source/drain regions of memory cells having avertical channel such that the channel regions of the vertical adjacentmemory cells may be inhibited from being electrically disconnected whenthe nonvolatile memory device is operated.

It is therefore a separate feature of an embodiment to provide anonvolatile memory device and a method for fabricating such a memorydevice in which the resistance of the source/drain region may be reducedin the memory cells relative to comparable conventional devices. Thus, acurrent can be increased in the memory cells storing data.

It is therefore a separate feature of an embodiment to provide anonvolatile memory device and a method for fabricating such a memorydevice in which, due to an interaction between fixed charges in thefixed charge layer and charges stored in the charge storage layer,diffusion of the charges stored in the charge storage layer of thememory device may be inhibited.

At least one of the above and other features and advantages may berealized by providing a nonvolatile memory device including a stackedstructure on a semiconductor substrate, the stacked structure comprisingconductive patterns and interlayer dielectric patterns alternatelystacked therein, a semiconductor pattern connected to the semiconductorsubstrate by passing through the stacked structure, a data storage layerbetween the semiconductor pattern and the conductive patterns, and afixed charge layer between the semiconductor pattern and the interlayerdielectric patterns, the fixed charge layer including fixed charges,wherein electrical polarity of the fixed charges is equal to electricalpolarity of majority carriers of the semiconductor pattern.

The semiconductor pattern may include a p-type semiconductor material,and the fixed charge layer may include elements generating positivefixed charges.

The elements generating the positive fixed charges include nitrogen (N),hydrogen (H), hafnium (HF), and/or zirconium (Zr).

The fixed charge layer may include silicon nitride (SiN), siliconoxynitride (SiON), hafnium oxide, and/or zirconium oxide.

The semiconductor pattern may include an n-type semiconductor material,and the fixed charge layer may include elements generating negativefixed charges.

The elements generating the negative fixed charges may include fluorine(F) and/or aluminum (Al).

The fixed charge layer may include aluminum oxide and/or aluminumoxynitride.

The semiconductor pattern may include a channel region adjacent to theconductive pattern and a channel connection region adjacent to the fixedcharge layer, and a number of majority carriers in the channelconnection region may be smaller than a number of majority carriers inthe channel region.

The data storage layer may extend on top surfaces and bottom surfaces ofthe conductive pattern.

The interlayer dielectric patterns may include an insulating materialhaving a dielectric constant smaller than a dielectric constant of amaterial of the fixed charge layer.

At least one of the above and other features and advantages may berealized by providing a method for fabricating a nonvolatile memorydevice, including alternately stacking a plurality of first materiallayers and a plurality of second material layers on a semiconductorsubstrate, forming first openings passing through the first and secondmaterial layers and exposing the semiconductor substrate, forming afixed charge layer on an inner wall of the first openings, the fixedcharge layer being adapted to generate fixed charges, formingsemiconductor patterns in the first openings, the semiconductor patternsextending from the semiconductor substrate to contact the fixed chargelayer, forming a second opening passing through the first and secondmaterial layers between the first openings, removing the first materiallayers and portions of the fixed charge layer contacting the firstmaterial layers to form gate regions exposing portions of thesemiconductor patterns and interlayer dielectric patterns, forming adata storage layer contacting the portions of the semiconductor patternsin the gate regions, respectively, and forming conductive patterns onthe data storage layer in the gate regions.

The semiconductor pattern may include a p-type semiconductor material,and the fixed charge layer may include elements generating positivefixed charges.

The elements generating the positive fixed charges may include nitrogen(N), hydrogen (H), hafnium (HF), and/or zirconium (Zr).

The semiconductor pattern may include an n-type semiconductor material,and the fixed charge layer may include elements generating negativefixed charges.

The elements generating the negative fixed charges may include fluorine(F) and/or aluminum (Al).

Forming the fixed charge layer may include performing a plasma processor an annealing process using a process gas including elements adaptedto generate the fixed charges.

Forming the fixed charge layer may include depositing an insulatinglayer including the elements adapted to generate the fixed charges.

Forming the fixed charge layer may include ion-implanting elementsgenerating the fixed charge.

Forming the data storage layer may include conformally forming the datastorage layer along surfaces of the semiconductor patterns and surfacesof the second material layers that are exposed by the gate regions.

Forming the conductive patterns may include forming a conductive layerfilling the second opening and the gate regions, and patterning theconductive layer to form the conductive patterns in the gate regions,respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages will become more apparent tothose of ordinary skill in the art by describing in detail exemplaryembodiments with reference to the attached drawings, in which:

FIG. 1 illustrates a schematic diagram of a nonvolatile memory deviceaccording to an embodiment;

FIG. 2 illustrates a structural diagram of a portion of the nonvolatilememory device of FIG. 1 according to an embodiment;

FIG. 3 illustrates a cross-sectional diagram of a portion of the memorycells of the nonvolatile memory device of FIG. 1;

FIG. 4 illustrates a structural diagram of a portion of the nonvolatilememory device of FIG. 1 according to another embodiment;

FIGS. 5, 6, 7, 8, 9, 10, 11, and 12 illustrate cross-sectional diagramsof resulting structures of stages of a method for fabricating anonvolatile memory device according to an embodiment;

FIG. 13 illustrates a block diagram of an exemplary memory systemincluding a nonvolatile memory device according to an embodiment;

FIG. 14 illustrates a block diagram of an exemplary memory cardincluding a nonvolatile memory device according to an embodiment; and

FIG. 15 illustrates a block diagram of an exemplary informationprocessing system equipped with a nonvolatile memory device according toan embodiment.

DETAILED DESCRIPTION

Korean Patent Application No. 10-2009-0093292, filed on Sep. 30, 2009,in the Korean Intellectual Property Office, and entitled: “NonvolatileMemory Device and Method for Fabricating the Same,” is incorporated byreference herein in its e

Exemplary embodiments of the inventive concept will be described belowin more detail with reference to the accompanying drawings. Theinventive concept may, however, be embodied in different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventiveconcept to those skilled in the art.

In the drawings, the dimensions of layers and regions may be exaggeratedfor clarity of illustration. It will be understood that when an elementsuch as a layer, film, region, or substrate is referred to as being “on”another element, it can be directly on the other element or interveningelements may also be present. Further, it will be understood that whenan element is referred to as being ‘under’ another element, it can bedirectly under, and one or more intervening elements may also bepresent. In addition, it will also be understood that when an element isreferred to as being ‘between’ two elements, it can be the only elementbetween the two elements, or one or more intervening elements may alsobe present. Like reference numerals refer to like elements throughoutthe specification.

In the following description, the technical terms are used only forexplain a specific exemplary embodiment while not limiting the inventiveconcept. The terms of a singular form may include plural forms unlessreferred to the contrary. The meaning of “include,” “comprise,”“including,” or “comprising,” specifies a property, a region, a fixednumber, a step, a process, an element and/or a component, but does notexclude other properties, regions, fixed numbers, steps, processes,elements and/or components. Additionally, in the following description,some elements may be illustrated in plural while some elements may beillustrated in singular, however, unless specified otherwise,embodiments may include not only more or less of the elements, but alsoa plurality of elements illustrated in singular or only one of theelements illustrated in plural.

Additionally, the embodiment in the detailed description will bedescribed with reference to sectional views and/or plan views as idealexemplary view of the inventive concept. Shapes of the exemplary viewsmay be modified according to manufacturing techniques and/or allowableerrors. Therefore, the embodiments of the inventive concept are notlimited to the specific shape illustrated in the exemplary views, butmay include other shapes that may be created according to manufacturingprocesses. For example, an etching region illustrated as angular mayhave a round shape or a certain curvature. Therefore, regionsexemplified in the drawings have general properties, and are used toillustrate a specific shape of a device region. Thus, this should not beconstrued as limiting the scope of the inventive concept.

Hereinafter, exemplary embodiments of the inventive concept will bedescribed in detail with reference to the accompanying drawings. Asemiconductor memory device according to embodiments may have athree-dimensional structure.

FIG. 1 illustrates a schematic diagram of a nonvolatile memory deviceaccording to an embodiment. FIG. 2 illustrates a structural diagram of aportion of the nonvolatile memory device of FIG. 1. FIG. 3 illustrates across-sectional diagram of a portion of the memory cells of thenonvolatile memory device of FIG. 1.

Referring to FIGS. 1 and 2, a three-dimensional semiconductor memorydevice according to an embodiment may include a common source line CSL,a plurality of bit lines BL0, BL1 and BL2, and a plurality of cellstrings CSTR disposed between the common source line CSL and the bitlines BL0 to BL2.

The common source line CSL may be a conductive thin film on asemiconductor substrate 100 or an impurity region in the semiconductorsubstrate 100. The bit lines BL0 to BL2 may be conductive patterns,e.g., metal lines, disposed over the semiconductor substrate 100. Thebit lines BL0 to BL2 may be two-dimensionally arranged. The plurality ofcell strings CSTR may be connected to the respective bit lines BL0 toBL2 in parallel. Thus, the cell strings CSTR may be two-dimensionallyarranged over the common source line CSL and/or the semiconductorsubstrate 100.

The respective cell strings CSTR may include a ground select transistorGST connected to the common source line CSL, a string select transistorSST connected to the bit lines BL0 to BL2, and a plurality of memorycell transistors MCT disposed between the ground and string selecttransistors GST and SST. The ground select transistor GST, and thestring select transistor SST, and the memory cell transistors MCT ofeach of the cell strings CSTR may be connected to each other in series.In addition, a ground select line GSL, a plurality of word lines WL0 toWL3, and a plurality of string select lines SSL, which may be disposedbetween the common source line CSL and the bit lines BL0 to BL2, may beused as gate electrodes of the ground select transistor GST, the memorycell transistors MCT, and the string select transistors SST,respectively.

All of the string select lines SSL may be arranged at a same distancefrom the semiconductor substrate 100. In embodiments in which the cellstrings CSTR include a plurality of memory cell transistors MCT, each ofthe memory cell transistors of the respective cell string CSTR may bearranged at a different distance from the semiconductor substrate 100.Respective ones of the memory cell transistors MCT of each of the cellstrings CSTR may be arranged in respective rows such that memory celltransistors MCT of each of the rows may be arranged a same distance fromthe semiconductor substrate 100. Further, respective ones of the memorycell transistors MCT of different ones of the cell strings CSTR that arearranged along a same row may be commonly connected to a respective oneof the word lines WL0 to WL3.

All of the ground select transistors GST may be disposed a same distancefrom the semiconductor substrate 100. The gate electrodes of the groundselect transistors GST may be commonly connected to the ground selectline GSL to be in an equipotential state. Similarly, the gate electrodesof the plurality of memory cell transistors MCT disposed atsubstantially a same distance, e.g., within same row, from the commonsource line CSL may also be commonly connected to the respective wordline WL0 to WL3 to be in an equipotential state. In embodiments in whichone cell string CSTR includes a plurality of the memory cell transistorsMCT, which may be arranged at different distances from the common sourceline CSL, multi-layered word lines WL0 to WL3 may be disposed betweenthe common source line CSL and the bit lines BL0 to BL2.

The cell strings CSTR may include a semiconductor pattern 200 verticallyextended from the semiconductor substrate 100 to be connected to the bitlines BL0 to BL2. The semiconductor pattern 200 may be formed topenetrate through the ground select line GSL and the word lines WL0 toWL3.

A data storage layer 230 may be disposed between the word lines WL0 toWL3 and the semiconductor pattern 200. According to an embodiment, thedata storage layer 230 may be a charge storage layer. For example, thedata storage layer 230 may be an insulating layer including a trapinsulating layer, a floating gate electrode, and/or conductive nanodots.

Referring to FIG. 2, a stack structure ST in which conductive patterns241 to 246 and interlayer dielectric patterns 121 to 126 are alternatelystacked may be disposed on the semiconductor substrate 100.

The semiconductor substrate 100 may be a semiconductor layer of a singlecrystal structure, and may include an impurity region 102 as a commonsource line. In this case, the semiconductor substrate 100 and theimpurity region 102 used as a common source line may be of differentconductive types.

The stack structure ST may include a plurality of conductive patterns241 to 246 and a plurality of interlayer dielectric patterns 121 to 126that may be vertically stacked. The interlayer dielectric patterns 121to 126 may be alternatively stacked between the conductive patterns 241to 246. The conductive patterns 241 to 246 of the stack structure ST maycorrespond to the ground select line GSL, word lines WL0 to WL3, and thestring select lines SSL and, e.g., may be stacked according to stackingsequence illustrated in FIG. 1.

The conductive patterns 241 to 246 may include conductive material,e.g., doped semiconductor, metals, metal nitrides, and/or metalsilicides. The conductive patterns 241 to 246 may be formed in adirection crossing a bit line 260. The conductive patterns 241 to 246may control electrical connections between the bit line 260 and thecommon source line (CSL of FIG. 1) by controlling a potential of thesemiconductor pattern 200. More specifically, the semiconductor pattern200 may be capacitively coupled to the conductive patterns 241 to 246and may form a MOS capacitor. In this case, a voltage applied to theconductive patterns 241 to 246 may variably control the potential of thesemiconductor pattern 200 adjacent to the conductive patterns 241 to246. The energy band of the semiconductor pattern 200 may be inversedaccording to the voltage applied to the conductive patterns 241 to 246.Accordingly, electrical connection between the bit line 260 and thecommon source line, e.g., impurity region 102, may be controlled by thevoltage applied to the conductive patterns 241 to 246.

The semiconductor pattern 200 may be connected to the semiconductorsubstrate 100 through the stack structure ST. The data storage layer 230may be disposed between the semiconductor pattern 200 and the conductivepatterns 241 to 246. A buried insulating layer 250 may be disposedbetween the stack structures ST adjacent to each other horizontally.Thus, the conductive patterns 241 to 246 horizontally adjacent to eachother may be electrically insulated. The bit line 260 may be disposed onthe plurality of semiconductor patterns 200 and may be arranged toextend along a direction crossing a direction along which the conductivepatterns 241 to 246 extend.

A dielectric layer may be disposed between the ground select line GST,e.g., respective ones of the conductive patterns, e.g., 241, and thesemiconductor pattern 200 and/or between the string selection lines SSL,e.g., respective ones of the conductive patterns, e.g., 246, and thesemiconductor pattern 200. The dielectric layer may correspond to aportion, e.g., one or more layers, of the data storage layer 230. Thatis, e.g., the data storage layer 230 may include, e.g., a plurality oflayers, and, e.g., one or more of such layers may be disposed betweenthe ground select line GST and the semiconductor pattern 200 and/orbetween the string select lines SST and the semiconductor pattern 200and may function as a gate insulating layer for a typical MOSFET and mayinclude, e.g., silicon oxide. More particularly, e.g., the dielectriclayer may be disposed between the ground select line GSL and thesemiconductor pattern 200 and/or between the string select lines SSL andthe semiconductor pattern 200 and may be used as a gate insulating layerof the ground select transistor GST or the string select transistorsSST, respectively. The gate insulating layer of the ground selecttransistor GST and/or the string select transistors SST may include asame material as at least a portion of the data storage layer 230 of thememory cell transistor MCT.

The ground and string select transistors GST and SST, and the memorycell transistors MCT may be a MOSFET using the semiconductor pattern 200as a channel region.

The semiconductor pattern 200 may include a single crystal semiconductorand/or a polycrystalline semiconductor. The semiconductor pattern 200may be an intrinsic semiconductor. The semiconductor pattern 200 mayextend vertically from to the semiconductor substrate 100. Thesemiconductor pattern 200 may have a circular or polygonal pillar shape.More particularly, the semiconductor pattern 200 may have a hollowcylindrical or a cup-like shape.

The semiconductor pattern 200 may be formed to be of the same conductivetype as the semiconductor substrate 100 contacting the semiconductorpattern 200. Thus, the semiconductor pattern 200 and the semiconductorsubstrate 100 may be electrically connected to each other. An insulatinglayer 210 may be buried in the semiconductor pattern 200. Also, athickness of the semiconductor pattern 200 may be smaller than a widthof a depletion region generated therein, or may be smaller than anaverage length of silicon grains forming polycrystalline silicon.

The semiconductor pattern 200 may include an impurity region 202 havinga different conductive type from the semiconductor pattern 200. Theimpurity region 202 may be in a region of the semiconductor connected tothe bit line 260.

The data storage layer 230 may extend on top surfaces and bottomsurfaces of the respective conductive patterns 241 to 246 between thesemiconductor pattern 200 and the conductive patterns 241 to 246.Specifically, the data storage layer 230 may be disposed between the topsurfaces of the respective conductive patterns 241 to 246 and the bottomsurfaces of the interlayer dielectric patterns 121 to 126, and may bedisposed between the bottom surfaces of the respective conductivepatterns 241 to 246 and the top surfaces of the interlayer dielectricpatterns 121 to 126.

The data storage layer 230 may include a charge storage layer. The datastored in the data storage layer 230 may be changed usingFowler-Nordheim tunneling caused by a voltage difference between thesemiconductor pattern 200 and the conductive patterns 241 to 246. Insome embodiments, the data storage layer 230 may be a thin film, e.g.,thin film for a phase-change memory or a variable resistance memory,capable of storing information using a different operating principle.

Referring to FIG. 3, the data storage layer 230 may include a chargetunneling layer 232 adjacent to the semiconductor pattern 200, a chargeblocking layer 236 adjacent to the conductive patterns 243 and 244, anda charge storage layer 234 between the charge tunneling layer 232 andthe charge blocking layer 236. The charge tunneling layer 232 mayinclude a material having a dielectric constant smaller than that of thecharge blocking layer 236. The charge storage layer 234 may be aninsulating thin film, e.g., silicon nitride, abundant in charge trapsites, or may be an insulating thin film including conductive particles.The charge blocking layer 236 may include silicon oxide, siliconnitride, silicon oxynitride, and/or a high dielectric layer, or may be amulti-layer thin film including a high dielectric layer. For example,the charge tunneling layer 232 may include silicon oxide. The chargestorage layer 234 may include silicon nitride. The charge blocking layer236 may include aluminum oxide.

Referring back to FIG. 2, a fixed charge layer 142 may be disposedbetween the semiconductor pattern 200 and the interlayer dielectricpatterns 121 to 126.

The fixed charge layer 142 may directly contact a surface of thesemiconductor pattern 200, and may include positive or negative fixedcharges. The fixed charge layer 142 may include a material includingelements that generate the positive or negative fixed charges. Theelements may be segregated into the semiconductor pattern 200 by heat.The electrical polarity of the fixed charges may be identical to that ofmajority carriers of the semiconductor pattern 200. The electricalpolarity of the fixed charges may vary with materials forming the fixedcharge layer 142. The material forming the fixed charge layer 142 may bea material having a dielectric constant smaller than that of theinterlayer dielectric patterns 121 to 126. Also, the fixed charge layer142 may have a thickness range from about several Å to about severaltens of nm. For example, the fixed charge layer 142 may have a thicknessequal to or smaller than that of the data storage layer 230.

Specifically, when the semiconductor pattern 200 includes a p-typesemiconductor material, the fixed charge layer 142 may include amaterial including elements that generate positive fixed charges. Forexample, elements generating positive fixed charges may include nitrogen(N), hydrogen (H), hafnium (Hf), and/or zirconium (Zr), and the fixedcharge layer 142 having the positive fixed charges may include siliconnitride (SiN), silicon oxynitride (SiON), hafnium oxide, and/orzirconium oxide.

On the other hand, when the semiconductor pattern 200 includes an n-typesemiconductor material, the fixed charge layer 142 may include amaterial including elements that generate negative fixed charges. Forexample, the elements generating negative fixed charges may includefluorine (F), phosphorus (P), and/or aluminum (Al), and the fixed chargelayer 142 having the negative fixed charges may include aluminum oxideand/or aluminum oxynitride.

Referring again to FIG. 3, a nonvolatile memory device may include thesemiconductor pattern 200 extending vertically relative to asemiconductor substrate 100, conductive patterns 243 and 244 disposed ona sidewall of the semiconductor pattern 200, and the fixed charge layer142 disposed between the conductive patterns 243 and 244. The datastorage layer 230 may be disposed between sidewalls of the conductivepatterns 243 and 244 and the semiconductor pattern 200. The interlayerdielectric patterns 122, 123, 124 may be disposed between the conductivepatterns 243 and 244.

The semiconductor pattern 200 may include a channel region 154 adjacentto the conductive patterns 243 and 244 and a channel connection region152 adjacent to the fixed charge layer 142. The fixed charge layer 142,as described above, may include positive or negative fixed chargesaccording to the conductive type of the semiconductor pattern 200. Anenergy level of the channel connection region 152 may be determined byfixed charge included in the fixed charge layer 142. Specifically, sincethe fixed charges included in the fixed charge layer 142 may generate anelectrostatic field, the channel connection region 152 adjacent to thefixed charge layer 142 may have an energy level based on the chargedensity or charge quantity of the fixed charges included in the fixedcharge layer 142. For example, the energy level of the channelconnection region 152 may be a depletion state or an inversion stateaccording to the charge density or the charge quantity of the fixedcharges included in the fixed charge layer 142.

Similarly, referring to FIG. 3, an energy level of the channel region154 may be variably determined by a voltage applied to the adjacentconductive pattern, e.g., 243, 244. When a voltage greater than athreshold voltage of a memory cell transistor is applied to theconductive patterns 243, 244, the channel region 154 may enter theinversion state to turn on the corresponding memory cell transistor.Unlike this, when a voltage smaller than the threshold voltage isapplied to the conductive patterns 243, 244, the channel region 154 mayenter the depletion state or accumulation state to turn off thecorresponding memory cell transistor.

According to an embodiment, the energy level of the channel region 154may be variably determined by the voltage applied to the respectiveconductive pattern 243, 244. However, when a number of the fixed chargesincluded in the fixed charge layer 142 is pinned, the energy level ofthe channel connection region 152 may be pinned.

As described above, the data storage layer 230 may horizontally extendfrom the sidewall of the conductive patterns 243 and 244 and may coverthe top surfaces and the bottom surfaces of the conductive patterns 243and 244. Such a horizontal extension of the charge storage layer 234 mayincrease a distance between the vertically stacked conductive patterns243 and 244. For example, referring to FIG. 3, a distance between thevertically stacked conductive patterns 243 and 244 may be TI+2™, whereTI is a thickness of the interlayer dielectric pattern, and TM is athickness of the data storage layer 230.

In some embodiments, the nonvolatile memory device may be configuredsuch that an electrical path between the bit line BL and the commonsource line CSL, described above with reference to FIG. 1, passesthrough the semiconductor pattern 200. For such an electrical path, thechannel regions 154 and the channel connection regions 152 in thesemiconductor pattern 200 may be connected to each other in series.

However, when the fixed charge layer 142 is absent, the electrical pathmay be difficult to complete due to the horizontal extension of thecharge storage layer 234 and an increase in an interval between theconductive patterns 243 and 244. Specifically, due to a fringe fieldfrom the conductive patterns 243 and 244, the channel region 154 may bevertically extended from the side surface of the correspondingconductive patterns 243 and 244 to have a length greater than athickness of the corresponding conductive patterns 243 and 244. However,the length of such an extension depends on a voltage applied to theconductive patterns 243 and 244. Accordingly, if the fixed charge layer142 is absent, and a voltage applied to the channel region 154 is small,then the channel region 154 adjacent to one conductive pattern may notbe connected in series to the channel region 154 adjacent to anotherconductive pattern, or an overlapping area therebetween may be reduced.In this case, the electrical path between the bit line and the commonsource line may not be completed, or may have low on-currentcharacteristics. These technical limitations may be overcome byemploying the fixed charge layer 142.

More particularly, e.g., when the quantity of the fixed charges includedin the fixed charge layer 142 is sufficient to make the channelconnection region 152 be in the inversion state, the channel region 154adjacent to one of the conductive patterns 243 and 244 may be connectedto the channel connection region 152, thereby completing the electricalpath. Even though the channel connection region 152 is in the depletionstate, the completion of the electrical path may be more easily achievedwhen the fixed charge layer 142 is present than when the fixed chargelayer 142 is absent.

Also, the fixed charge layer 142 may include fixed charges havingelectrical polarity that may contribute to completion of the electricalpath or inversion of the channel connection region 152. For example, theelectrical polarity of the fixed charges may be identical to theelectrical polarity of majority carriers of the semiconductor pattern200.

Specifically, when positive fixed charges are generated in the fixedcharge layer 142, electrons may accumulate in the channel connectionregion 152. On the other hand, when negative fixed charges are generatedin the fixed charge layer 142, holes may accumulate in the channelconnection region 152. Such a channel connection region 152 may be usedas source/drain region of the memory cell transistor MCT. Also,vertically adjacent memory cells may share the channel connection region152 induced by the fixed charge layer 142.

The resistance of the channel connection region 152 may be inverselyproportional to a density of the fixed charges in the fixed charge layer142, and may be varied by controlling a quantity of the elementsgenerating the fixed charges. As the resistance of the channelconnection region 152 decreases, a cell current between the bit line BLand the common source line CSL may increase progressively duringoperation of the nonvolatile memory device.

Due to the fixed charges in the fixed charge layer 142, the number ofmajority carriers in the channel connection region 152 may be smallerthan that of the channel region 154 in a non-inversed state.Accordingly, when a certain voltage is applied to the conductivepatterns 243 and 244 to invert the channel regions 154, electricalconnection characteristics between adjacent channel regions 154 may beimproved.

FIG. 4 illustrates a structural diagram of a portion of the nonvolatilememory device of FIG. 1 according to another embodiment. The exemplarynonvolatile memory device illustrated in FIG. 4 substantiallycorresponds to the exemplary nonvolatile memory device illustrated inFIGS. 2 and 3, and thus, only differences between the exemplaryembodiment of FIGS. 2 and 3, and the exemplary embodiment of FIG. 4 willbe described below.

Referring to FIG. 4, a stack structure ST′ may have a linear shape overa semiconductor substrate 100. A plurality of the semiconductor patterns200 may be disposed on a sidewall of one stack structure ST′. Thesemiconductor patterns 200 may have a vertical linear shape with respectto the semiconductor substrate 100, and may be disposed to be spacedfrom a sidewall of the stack structure ST′ by a certain interval. Aburied insulating layer 300 may be disposed between the semiconductorpatterns 200 crossing the sidewall of one stack structure ST′. Also, thesemiconductor patterns 200 on adjacent ones of the stack structures ST′may be disposed to face each other. A space between the semiconductorpatterns 200 may be filled with an insulating layer 210. That is, theburied insulating layer 300 and the insulating layer 210 may be formedbetween adjacent ones of the semiconductor patterns 200.

FIGS. 5, 6, 7, 8, 9, 10, 11, and 12 illustrate cross-sectional diagramsof resulting structures of stages of a method for fabricating anonvolatile memory device according to an embodiment. Hereinafter, amethod for fabricating a nonvolatile memory device according toembodiment will be described in detain with reference to FIGS. 5 through12.

Referring to FIG. 5, a plurality of thin film structures, e.g., firstthin film structure 110 and second thin film structure 120 may bealternatively stacked on the semiconductor substrate 100. Moreparticularly, the first thin film structure may include a plurality offirst material layers 111 to 116, and the second thin film structure mayinclude a plurality of second material layers 121 to 126, and the firstmaterial layers 111 to 116 and the second material layers 121 to 126 maybe alternately stacked on the semiconductor substrate 100. Referring toFIG. 5, e.g., the first thin film structure 110 may include theplurality of first material layers 111 to 116 that are spaced from eachother and the second thin film structure 120 may include the pluralityof second material layers 121 to 126 interposed between the firstmaterial layers 111 to 116 of the first thin film structure 110. Thatis, the first material layers 111 to 116 of the first thin filmstructure 110 and the second material layers 121 to 126 of the secondthin film structure 120 may be alternatively arranged in a stack.

The number of the first and second materials 111 to 116 and 121 to 126forming the thin film structures 110 and 120 may be varied based on thememory capacity.

The first and second thin film structures 110 and 120 may be formed ofthin films having different characteristics, e.g., different etch ratesin an isotropic etching process and/or different etch rates in ananisotropic etching process. For example, the first material layers 111to 116 may be formed of materials that may be selectively removed whileminimizing etching of the second material layers 121 to 126. Forexample, the first and second material layers 111 to 116 and 121 to 126may include silicon oxide undoped with impurities, silicon oxide dopedwith impurities, silicon nitride, silicon oxynitride, and/or adielectric layer having a low dielectric constant, e.g., SiOC and SiOF.

Also, a material layer to be removed during a subsequent process may befirst formed such that a lower select line to be formed during asubsequent process may effectively control potentials of thesemiconductor pattern 200 and the semiconductor substrate 100.

Thereafter, first openings 130 may be formed in the thin film structures110 and 120 to expose an upper surface of the semiconductor substrate100. The first openings 130 may have a hole or trench shape.Specifically, forming of the first openings 130 may include forming amask pattern (not shown) defining planar positions of the openings 130on the thin film structure 110 and 120 and anisotropically etching thethin film structures 110 and 120 using the mask pattern as an etch mask.As the first openings 130 are formed, sidewalls of the first and secondthin film structures 110 and 120 may be exposed.

Referring to FIG. 6, the fixed charge layer 140 may be formed on asurface of the first and second material layers 111 to 116 and 121 to126 exposed to the first openings 130.

The fixed charge layer 140 may be formed of a material includingelements generating positive or negative fixed charges according to theconductive type of the semiconductor pattern 200. The fixed charge layer140 may have a very small thickness of, e.g., about several nm to aboutseveral tens of nm.

Specifically, when the semiconductor pattern 200 is a p-type, the fixedcharge layer 140 may be formed of a material including elementsgenerating positive fixed charges. For example, elements generating thepositive fixed charges may include nitrogen (N), hydrogen (H), hafnium(Hf), and/or zirconium (Zr).

On the other hand, when the semiconductor pattern 200 is an n-type, thefixed charge layer 140 may be formed of a material including elementsgenerating negative fixed charges. For example, elements generating thenegative fixed charges may include fluorine (F), phosphorous (P), and/oraluminum (Al).

The fixed charge layer 140 may be formed by a plasma process or anannealing process using a process gas including elements generatingfixed charges. For example, the fixed charge layer 140 having thepositive fixed charges may be formed by the plasma process or theannealing process using a process gas including, e.g., N₂, N₂O, NO, NH₃,and/or H₂. Also, the density of the fixed charges of the fixed chargelayer 140 may be controlled by adjusting the duration of the plasmaprocess and the annealing process. As the density of the fixed chargesincreases, the resistance of the channel connection region 152 inducedby the fixed charge layer 140 may be reduced. That is, the resistance ofthe channel connection region 152 provided to the source/drain region oftransistors may be reduced, thereby increasing an on-state cell current.

Also, as another method for forming the fixed charge layer 140, thefixed charge layer 140 may be formed by depositing an insulating layerhaving elements generating fixed charges. For example, the fixed chargelayer 140 including positive fixed charges may be formed by depositingsilicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide, and/orzirconium oxide. The fixed charge layer 140 including negative fixedcharges may be formed by depositing aluminum oxide and/or aluminumoxynitride.

As another method for forming the fixed charge layer 140, the fixedcharge layer 140 may be formed by ion-implanting elements generating thefixed charges into the surface of the first and second material layers111 to 116 and 121 to 126.

Referring to FIG. 7, the semiconductor pattern 200 may be formed to beextended from the semiconductor substrate 100 and contact the fixedcharge layer 140. The semiconductor pattern 200 may be formed of thesame material as the semiconductor substrate 100.

The semiconductor pattern 200 may be conformally formed along an innerwall of the first opening 130. That is, the semiconductor pattern 200may be formed to have, e.g., a hollow cylindrical shape or a well shape.An inner space of the semiconductor pattern 200 may be filled with theinsulating layer 210. In embodiments, the thickness of the semiconductorpattern 200 may be smaller than the width of a depletion regiongenerated therein, and/or may be smaller than an average length ofsilicon grains forming polycrystalline silicon.

The semiconductor pattern 200 may have a circular or polygonal pillarshape that fills the first openings 130. When the first openings 130have a trench shape, the plane of the semiconductor pattern 200 may belinear.

The semiconductor pattern 200 may include, e.g., polycrystalline oramorphous silicon. A discontinuous boundary surface of a crystalstructure may be formed between the semiconductor substrate 100 and thesemiconductor pattern 200. The semiconductor substrate 100 and thesemiconductor pattern 200 may be silicon of a single crystal structuresmoothly connected without a crystal defect.

The semiconductor pattern 200 may be formed using Chemical VaporDeposition (CVD) or Atomic Layer Deposition (ALD). The semiconductorpattern 200 may also be formed by a Selective Epitaxial Growth (SEG)process using the semiconductor substrate 100 exposed by the firstopening 130 as a seed layer. The semiconductor pattern 200 may also beformed by a Laser-induce Epitaxial Growth (LEG) process that grows anamorphous semiconductor layer in the first openings 130, and thenirradiates a laser beam such as an excimer laser on the amorphoussemiconductor layer to crystallize the semiconductor layer.

Referring to FIG. 8, second openings 220 may be formed in the thin filmstructures 110 and 120 to expose the upper surface of the semiconductorsubstrate 100. The second openings 220 may be formed by performing atypical photolithography and etching processes on the first and secondthin film structures 110 and 120. The second openings 220 may be formedin a linear shape between the first openings 130 in which thesemiconductor patterns 200 have been formed. The second openings 220 mayexpose the surface of the semiconductor substrate 100 in a linear shape.As the second openings 220 are formed, sidewalls of the first and secondmaterial layers 111 to 116 and 121 to 126 of the thin film structures110 and 120 may be exposed to the second opening 220.

The impurity region 102 may then be formed in the semiconductorsubstrate 100 exposed by the second opening 220. In some embodiments,the impurity region 102 may be formed before the thin film structures110 and 120 are formed on the semiconductor substrate 100.

Referring to FIG. 9, the first material layers 111 to 116 exposed by thesecond opening 220 may be removed. Thus, gate regions GR may be formedbetween the stacked second material layers 121 and 126 to expose thesidewall of the semiconductor pattern 200.

Removal of the first material layer 111 to 116 may be performed using anetch recipe having etch selectivity with respect to the second materiallayers 121 to 126 and the semiconductor pattern 200. For example, thefirst material layers 111 to 116 may be removed using an etchant for awet-etching of the first material layers 111 to 116. Removal of thefirst material layers 111 to 116 may be performed using either adry-etching or a wet-etching, but may be performed by an isotropicetching.

When the first material layers 111 to 116 are removed, the fixed chargelayer 142 contacting the semiconductor pattern 200 may also be removedby an over-etching. Thus, the fixed charge layers 142 may be formedbetween the semiconductor pattern 200 and the second material layers 121to 126. On the other hand, when portions of semiconductor pattern 200adjacent to the first material layers 111 to 116 are exposed by theisotropic etching process, a portion of the fixed charge layer 142adjacent to the second material layers 121 to 126.

Referring to FIG. 10, the data storage layer 230 may be formed on aresulting structure in which the gate regions GR are formed.

The data storage layer 230 may be conformally formed along the surfaceof the thin film structure 120 in which the gate regions GR exposingportions of the sidewall of the semiconductor pattern 200 are formed.That is, the data storage layer 230 may be formed on the surface of thesemiconductor pattern 200 exposed to the gate regions GR and the surfaceof the second material layers 121 to 126 exposed to the gate regions GR.When the semiconductor pattern 200 has a hollow cylindrical shape, thedata storage layer 230 may be formed to surround the circumference ofthe semiconductor pattern 200.

The data storage layer 230 may include the charge tunneling layer 232,the charge storage layer 234, and the charge blocking layer 236 asdescribed above. In such cases, the charge tunneling layer 232 may beformed to cover the sidewall of the semiconductor pattern 200 exposed bythe gate region GR. The charge storage layer 234 and the charge blockinglayer 236 may be sequentially formed on the charge tunneling layer. Thecharge tunneling layer 232, the charge storage layer 234, and the chargeblocking layer 236 may be formed using a thin film formation method,e.g., CVD or ALD, which provides excellent step coverage. Since thesidewall of the semiconductor pattern 200 is exposed by the gate regionsGR, the charge tunneling layer may be formed by directly performing athermal oxidation process on the exposed surface of the semiconductorpattern 200.

For example, the charge tunneling layer 232 may be formed of siliconoxide (SiO2) and/or silicon oxynitride (SiON). The charge tunnelinglayer 232 may be formed of a complex layer in which a high dielectricmaterial such as Al₂O₃, HfO₂ ZrO₂, La₂O₃, Ta₂O₃, TiO₂, SrTiO₃(STO),and/or (Ba,Sr)TiO₃(BST) and combination thereof are stacked. In suchcases, the charge tunneling layer 232 may be formed of a material havinga dielectric constant smaller than the charge blocking layer 236.

The charge storage layer 234 may include at least one of an insulatingthin layer abundant in charge trap sites such as silicon nitride layerand/or silicon oxynitride, an insulating thin layer including nano dots,and a conductive thin layer that may be locally patterned to serve as afloating electrode.

For example, the charge blocking layer 236 may be formed of a complexlayer in which a high dielectric material such Al₂O₃, HfO₂ZrO₂, La₂O₃,Ta₂O₃, TiO₂, SrTiO₃(STO), and/or (Ba,Sr)TiO₃(BST) and combinationthereof are stacked. In such cases, the charge tunneling layer 232 mayare stacked.

The data storage layer 230 is not limited to a thin layer for storingelectric charges. The data storage layer 240 may be, e.g., a thin layerfor a phase-change memory or a variable-resistance memory, capable ofstoring data using a different operating principle.

Referring to FIG. 11, the conductive patterns 241 to 246, hereinafteralso referred to as gate electrodes 241 to 246, may be formed betweenthe vertically stacked second material layers 121 to 126.

Specifically, forming the gate electrodes 241 to 246 may include forminggate regions GR on the resulting structure in which the data storagelayer 230 is formed, depositing a gate conductive layer filling the gateregions GR and the second opening 220, and reforming the second opening220 by patterning the gate conductive layer. Thus, the gate electrodestructure 240 in which the gate electrodes 241 to 246 are verticallystacked may be formed on the semiconductor substrate 100.

Forming the gate conductive layer may be performed using thin layerformation technologies that provide excellent step coverage. The gateconductive layer may include polycrystalline silicon layer doped withimpurities, silicide layers, (e.g., titanium silicide, cobalt silicide,and nickel silicide), metal layers (e.g., tungsten and copper), and/ormetal nitride layers (e.g., titanium nitride and tantalum nitride).

Forming the second opening 220 may include forming a mask pattern (notshown) and anisotropically etching using the mask pattern as an etchmask. In such cases, the second opening 220 may be reformed to exposethe data storage layer 230 on the sidewall of the second material layers121 to 126 to form the electrically separated gate electrodes 241 to246. The anisotropic etching of the gate conductive layer may beperformed such that the data storage layer 230 on the sidewall of thesecond material layers 241 to 246 is also removed. Thus, the gateelectrodes 241 to 246 may be locally formed between the second materiallayers 121 to 126 that are vertically adjacent to each other. The datastorage layer 230 may also be locally formed between the second materiallayers 121 to 126.

As the second opening 220 is reformed, gate electrodes 241 to 246 havingan independently linear shape may be formed between the second materiallayers 121 to 126. The gate electrodes 241 to 246 having the linearshape may be three-dimensionally disposed on the semiconductor substrate100.

Next, the buried insulating layer 250 may be buried in the reformedsecond opening 220 to insulate the gate electrodes 241 to 246 that arehorizontally adjacent to each other. That is, the buried insulatinglayer 250 having a sufficient thickness may be deposited to fill thereformed second opening 220, and may be planarized until an uppersurface of the semiconductor pattern 200 is exposed.

Thereafter, the impurity region 202 may be formed on the semiconductorpatterns 200 by ion-implanting impurities of an opposite type to theconductive type of the semiconductor pattern 200.

Referring to FIG. 12, the bit lines 260 may be formed to be connected tothe semiconductor pattern 200.

The bit lines 260 may be formed to cross the gate electrodes 241 to 246over the stack structure in which the gate electrodes 241 to 246 and thesecond material layers 121 to 126 are alternately stacked. The bit lines260 may be electrically connected to the upper surfaces of thesemiconductor patterns 200 through a direct contact or a contact plug(not shown).

The bit lines 260 may be formed by depositing a conductive layer on thestack structure in which the gate electrodes 241 to 246 and the secondmaterial layers 121 to 126 are alternately stacked and patterning theconductive layer in a linear form. The bit lines 260 may also beconnected to the semiconductor pattern 200 through a direct contact or acontact plug.

As described above with regard to FIG. 5, when the first opening 130 isformed in a trench shape, the semiconductor layer in the first openings130 may have a linear plane. In this case, the process of forming thesemiconductor pattern 200 by patterning the semiconductor layer beforethe bit lines 260 are formed may be further included. That is, after thegate electrodes 241 to 246 are formed, a mask pattern crossing the gateelectrodes 241 to 246 may be formed, and then the semiconductor layer inthe first opening 130 may be etched using the mask pattern as an etchmask. Thus, the semiconductor patterns 200 that are spaced from eachother may be formed in the first opening 130.

FIG. 13 illustrates a block diagram of an exemplary memory systemincluding a nonvolatile memory device according to an embodiment.

Referring to FIG. 13, a memory system 1100 may be applied to PDAs,portable computers, web tablets, wireless phones, mobile phones, digitalmusic players, memory cards, or other devices capable ofsending/receiving data in wireless environments.

The memory system 1100 may include a controller 1110, an input/outputdevice 1120 such as keypad, keyboard, and display, a memory 1130, aninterface 1140, and a bus 1150. The memory 1130 and the interface 1140may communicate with each other through the bus 1150.

The controller 1110 may include one or more microprocessor, a digitalsignal processor, a microcontroller, or other similar processingdevices. The memory 1130 may be used to store commands performed by thecontroller 1110. The input/output device 1120 may receive data orsignals from the outside of the system 1100, or may send data or signalsto the outside of the system 1100. For example, the input/output device1120 may include a keyboard, a keypad, and a display device.

The memory 1130 may include nonvolatile memory devices according toembodiments. The memory 1130 may further include different memories,freely-accessible volatile memories, and other memories.

The interface 1140 may serve to send data to a communication network, orreceive data from the communication network.

FIG. 14 illustrates a block diagram of an exemplary memory cardincluding a nonvolatile memory device according to an embodiment.

Referring to FIG. 14, a memory card 1200 for supporting high-capacitydata storage may include a flash memory device 1210 according to anembodiment. The memory card 1200 may include a memory controller 1220controlling overall data exchanges between a host and the flash memorydevice 1210.

An SRAM 1221 may be used as an operating memory of a processing unit1222. A host interface 1223 may include a data exchange protocol of ahost connected to the memory card 1200. An error correction block 1224may detect and correct errors included in data read out from a multi-bitflash memory device 1210. A memory interface 1225 may interface with theflash memory device 1210. The processing unit 1222 may perform overallcontrol operations of the memory controller 1220 for data exchanges.Although not shown, it will be apparent to persons skilled in the artthat the memory card 1200 according to the embodiment may furtherinclude a ROM (not shown) for storing code data for interfacing with thehost.

The flash memory device 1210 and the memory card 1200 or the memorysystem 1100 according to the embodiments may provide a highly-reliablememory system through the flash memory device 1210 in which erasecharacteristics of a dummy cell may be improved. Particularly, the flashmemory device may be used in a memory system such as Solid State Disks(SSDs) that are widely used in recent years. In this case, read errorscaused by the dummy cell can be blocked, thereby implementinghighly-reliable memory systems.

FIG. 15 illustrates a block diagram of an exemplary informationprocessing system equipped with a nonvolatile memory device according toan embodiment.

Referring to FIG. 15, a flash memory system 1310 may be mounted in aninformation processing system 1300 such as mobile devices or desktopcomputers. The information processing system 1300 may include a modem1320, a central processing unit (CPU) 1330, a RAM 1340, and a userinterface 1350. The flash memory system 1310 may be configured to besubstantially identical to the memory system or the flash memory systemdescribed above. The flash memory system 1310 may store data process bythe CPU 1330 or external data. Here, the flash memory system 1310 may beconfigured with an SSD. In this case, the information processing system1300 may stably store large data in the flash memory system. Withenhancement of reliability, the flash memory system 1310 may reduceresources necessary for the error correction, thereby providing theinformation processing system 1300 with a high-rate data transfercapability. Although not shown, it is apparent to those skilled in theart that the information processing system 1300 may further includeapplication chipsets, camera image processors (CISs), and I/O devices.

A flash memory device or a memory system according to an embodiment maybe mounted in various types of packages. Examples of the packages of theflash memory device or the memory system include Package on Package(PoP), Ball Grid Arrays (BGA), Chip Scale Packages (CSP), Plastic LeadedChip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die in WafflePack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-linePackage (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad FlatPack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink SmallOutline Package (SSOP), Thin Small Outline Package (TSOP), System InPackage (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package(WFP), and Wafer-level Processed Stack Package (WSP).

In a nonvolatile memory device and a method for fabricating the sameaccording to an embodiment, since a channel connection region induced bya fixed charge layer is provided to the source/drain regions of memorycells having a vertical channel, the channel regions of the verticaladjacent memory cells may be inhibited from being electricallydisconnected when the nonvolatile memory device is operated.

Also, the resistance of the source/drain region may be reduced in thememory cells. Thus, a current can be increased in the memory cellsstoring data.

In addition, due to an interaction between fixed charges in the fixedcharge layer and charges stored in the charge storage layer, diffusionof the charges stored in the charge storage layer may be inhibited.

Exemplary embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation.Accordingly, it will be understood by those of ordinary skill in the artthat various changes in form and details may be made without departingfrom the spirit and scope of the present invention as set forth in thefollowing claims.

1.-10. (canceled)
 11. A method for fabricating a nonvolatile memorydevice, comprising: alternately stacking a plurality of first materiallayers and a plurality of second material layers on a semiconductorsubstrate; forming first openings passing through the first and secondmaterial layers and exposing the semiconductor substrate; forming afixed charge layer on an inner wall of the first openings, the fixedcharge layer being adapted to generate fixed charges; formingsemiconductor patterns in the first openings, the semiconductor patternsextending from the semiconductor substrate to contact the fixed chargelayer; forming a second opening passing through the first and secondmaterial layers between the first openings; removing the first materiallayers and portions of the fixed charge layer contacting the firstmaterial layers to form gate regions exposing portions of thesemiconductor patterns and interlayer dielectric patterns; forming adata storage layer contacting the portions of the semiconductor patternsin the gate regions, respectively; and forming conductive patterns onthe data storage layer in the gate regions.
 12. The method as claimed inclaim 11, wherein the semiconductor pattern includes a p-typesemiconductor material, and the fixed charge layer includes elementsgenerating positive fixed charges.
 13. The method as claimed in claim12, wherein the elements generating the positive fixed charges includenitrogen (N), hydrogen (H), hafnium (HF), and/or zirconium (Zr).
 14. Themethod as claimed in claim 11, wherein the semiconductor patternincludes an n-type semiconductor material, and the fixed charge layerincludes elements generating negative fixed charges.
 15. The method asclaimed in claim 14, wherein the elements generating the negative fixedcharges include fluorine (F) and/or aluminum (Al).
 16. The method asclaimed in claim 11, wherein forming the fixed charge layer includesperforming a plasma process or an annealing process using a process gasincluding elements adapted to generate the fixed charges.
 17. The methodas claimed in claim 11, wherein forming the fixed charge layer includesdepositing an insulating layer including the elements adapted togenerate the fixed charges.
 18. The method as claimed in claim 11,wherein forming the fixed charge layer includes ion-implanting elementsgenerating the fixed charge.
 19. The method as claimed in claim 11,wherein forming the data storage layer includes conformally forming thedata storage layer along surfaces of the semiconductor patterns andsurfaces of the second material layers that are exposed by the gateregions.
 20. The method as claimed in claim 11, wherein forming theconductive patterns comprises: forming a conductive layer filling thesecond opening and the gate regions; and patterning the conductive layerto form the conductive patterns in the gate regions, respectively.